1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device in which input circuits thereof can consume less power.
Recently, data transfer rates have been increased year by year because of the development of high-speed CPUs. In order to support the increased rates, there is a trend to broaden the width of data buses so that the number of the input circuits can be increased. For this reason, it is required to prevent the input circuits, which are not supplied with input signals and should not be activated, from consuming unnecessary power as much as possible.
2. Description of the Related Art
FIG. 1 and FIGS. 2A and 2B are block diagrams showing two examples of a conventional semiconductor integrated circuit device.
As shown in FIG. 1, a clock CLK, a clock enable signal CKE and a chip select signal CS are externally applied to a clock generating circuit 10, input buffers 12 and 14, respectively. A command signal, an address signal and a data signal are externally applied to input circuits 16, 18 and 20, respectively. When the clock enable signal CKE is maintained at a low level, the clock generating circuit 10 takes the clock CLK therein to generate an internal clock CLK and supply it to the input buffer 14 and the input circuits 16, 18 and 20, respectively. These circuits are thereby activated to be available to operate.
A timing-regulation portion within the clock generating circuit 10 may be, for example, a DLL (Delay Locked Loop) circuit. A command outputted from the input circuit 16 is applied to a command decoder 22.
As shown in FIG. 2A, the input circuits 14, 16, 18 and 20 each include an input interface portion 22 and a synchronous portion 23 which are shown in FIG. 2B. The input interface portion 22 is supplied with the clock enable signal CKE from the input buffer 12 so as to perform activation control.
FIG. 3 shows a timing chart of the signals at the time of a read operation according to the conventional device. FIG. 4 shows a timing chart of the signals at the time of a write operation according to the conventional device.
In the conventional device, the input circuits 16, 18 and 20 is activated during a low-level period of the clock enable signal CKE as shown in FIGS. 3 and 4. In fact, it is desired that these input circuits 16, 18 and 20 are activated only when the chip select signal CS is maintained at the low level. Hence, there is a problem in the conventional device that the period during which the input circuits 16, 18 and 20 are activated is too long, and as a result, the input circuits 16, 18 and 20 consume unnecessary power.
Further, in the conventional devices, the activation of the input circuits 16, 18 and 20 is performed in synchronism with that of the clock generating circuit 10. For this reason, in a case where the clock generating circuit 10 needs to be activated so as to activate, for example, output circuits (not shown), once the clock generating circuit 10 is activated, the input circuits 16, 18 and 20 are synchronously activated even if there is no command signal, address signal or data input signal taken therein. Hence, there is a problem in the conventional device that the input circuits 16, 18 and 20 are unnecessarily activated in such a case, and as a result unnecessary power is consumed.
It is a general object of the present invention to provide a semiconductor integrated circuit device in which the above problems are eliminated.
A more specific object of the present invention is to provide a semiconductor integrated circuit device in which input circuits thereof consumes less power.
The above objects of the present invention are achieved by a semiconductor integrated circuit device comprising: a power-down generating circuit for generating a power-down control signal in response to a power-down signal supplied externally; a clock generating circuit receiving an external clock for generating internal clocks and being inactivated in response to the power-down control signal; a chip select circuit for generating an input enable signal in response to a chip select signal externally supplied and being inactivated in response to the power-down control signal; and an input circuit receiving input signals supplied externally in synchronism with the internal clock activation and inactivation of said input circuit being controlled in response to the input enable signal and the power-down control signal.
Accordingly, since the input signal externally supplied is received in synchronism with the internal clock based on the input enable signal and the power-down control signal, even during the time of the power-down control signal indicating the power-on, the input circuit can be inactivated by the input enable signal. Hence, the power consumption can be reduced.